1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor circuit device including a metal oxide semiconductor (MOS) transistor and a polysilicon capacitor element.
2. Description of the Related Art
The following two methods have been mainly employed to manufacture a semiconductor circuit device formed on a semiconductor substrate and including at least a MOS transistor and a capacitor element as basic elements.
In method A, a semiconductor substrate is used as a lower electrode and a polysilicon film is used as an upper electrode. In this case, the polysilicon film serving as the upper electrode is provided in common with a gate electrode of the MOS transistor, and a capacitor film (insulator or dielectric body sandwiched between two conductors) is provided in common with a gate insulating film. Accordingly, with addition of few steps, a capacitor element may be added to a semiconductor circuit device including a MOS transistor.
In method B, polysilicon films are used as both of the lower and upper electrodes. In this case, one of the lower and upper electrodes is provided in common with the electrode of the MOS transistor. However, addition of the capacitor element to the semiconductor circuit device including the MOS transistor creates a need to add a step of forming a capacitor film and one of the polysilicon films.
In the method B the number of steps is increased compared to the method A. Instead, there are such merits that the fixation of the potential of the lower electrode to that of the semiconductor substrate, and the generation of a large junction capacitance due to electrical separation from the semiconductor substrate with the use of a PN junction can be avoided. Further, there are such other merits that the capacitor film may be set independently from the gate insulating film of the MOS transistor, and an occupied area may be overwhelmingly reduced by laminating a capacitor element on the capacitor element formed in the method A.
In some cases addition of a resistor element to the semiconductor circuit device is necessary and the resistor element is formed of a polysilicon film different from that of the gate electrode (for example, see Japanese Patent No. 2967265). In those cases, application of the polysilicon film used in the resistor element as one electrode of the capacitor element enables addition of the capacitor element of the method B with few additional steps. As described above, in view of the merits and the number of steps, a more suitable manufacturing method for the semiconductor circuit device is selected.
As for a semiconductor device including a MOS transistor, a resistor element, and a capacitor element, an invention aimed for reduction of the number of steps and improvement of its characteristics has been disclosed (for example, see Japanese Patent No. 2705476).
First, problems exemplified in Japanese Patent No. 2967265 are described with reference to FIG. 3. A semiconductor circuit device illustrated in FIG. 3 includes a MOS transistor and a polysilicon resistor film 103. The MOS transistor includes a gate electrode formed of a first polysilicon film 102, and source/drain (S/D) regions 108. The polysilicon resistor film 103 is a film formed in a step different from a step of forming the polysilicon film 102 which forms the gate electrode. Accordingly those two polysilicon films can be used to form a polysilicon capacitor element. In this case, a step of forming a photomask and implanting impurities for reduction in resistance of a contact region of the polysilicon resistor film 103 may be provided in common with a step of implanting high concentration impurities for formation of the gate electrode and the S/D regions of the MOS transistor. Further, a step for reduction in resistance for the upper electrode of the capacitor element formed of the two polysilicon films may be provided in common therewith. However, it is necessary to add a step for photomask formation and a step for high concentration impurity implantation, which is dedicated for reduction in resistance of the lower electrode of the capacitor element. This addition of steps is a problem. The addition of steps increases manufacturing cost inevitably.
Next, problems exemplified in Japanese Patent No. 2705476 are described with reference to FIG. 4. A semiconductor device illustrated in FIG. 4 includes a MOS transistor, a polysilicon resistor film 103, and a polysilicon capacitor element. The MOS transistor includes a gate electrode formed of a first polysilicon film 102 and a refractory material 111, S/D regions 108, and LDD regions 109. The polysilicon resistor film 103 is formed of a polysilicon film which is formed simultaneously with the first polysilicon film 102. The polysilicon capacitor element includes a lower electrode 103a of a polysilicon capacitor, which is formed of the first polysilicon film 102, an upper electrode 103b of the polysilicon capacitor, which is formed of the refractory material 111, and a capacitor film 107. This semiconductor device has a feature in that a single polysilicon layer may be used to form the MOS transistor, the resistor film, and the capacitor element. Accordingly the manufacturing steps can be simplified by the step of forming the second polysilicon film. However, considering the number of steps for impurity implantation, it is necessary to additionally perform high concentration impurity implantation twice for forming an N-type gate electrode and a P-type gate electrode of the MOS transistors between the step of forming the polysilicon film and the step of forming the refractory material. The number of steps may be reduced by performing impurity implantation of the lower electrode of the capacitor element in common with the above-mentioned high concentration impurity implantation, by performing impurity implantation of the resistor element in common therewith, or, in a case where high resistance is necessary, by implanting low concentration impurities into the entire surface and then overwriting implantation of high concentration impurities. However, even in this case, at least two times of high concentration impurity implantation are necessary. Further, aside from this, in order to form the S/D regions, at least two times of high concentration impurity implantation are necessary. In other words, in total, at least four times of high concentration impurity implantation steps are necessary. As described above, more than the benefits of step simplification by providing the polysilicon film in common, the increase of the number of steps becomes a problem. The increase of the number of steps also causes the increase of the manufacturing cost.
Further, an LDD structure having side walls are generally used to construct a MOS transistor. However, when the MOS transistor having the LDD structure is used as a normally-off transistor for electrostatic discharge protection, it is known that electrostatic discharge protection capability is deteriorated compared to the case of using a so-called conventional type MOS transistor without the LDD structure. Then it is necessary to increase the size of the transistor when the MOS transistor having the LDD structure is used as the normally-off transistor for electrostatic discharge protection. Here, requirement of additional steps in order to form the conventional type MOS transistor prevents usage of the conventional type MOS transistor which can be reduced in size, which has been a problem.